The logic states of digital signals are typically discriminated by circuits that operate to provide an output signal which follows a hysteresis function of an input signal. For example, in digital TTL circuits, a logic signal is considered "high" only when its voltage level is above a threshold (for example, 2 volt). However, to return to a "low" logic level, the voltage of the signal would have to drop below another threshold (for example, 0.8 volt). The separation between the two thresholds is used to prevent unexpected level switching due to noise.
The growing use of CMOS technology in digital circuits has led to an increasing demand for efficient CMOS logic level discriminators. One such discriminator is disclosed in U.S. Pat. No. 4,656,374, issued to A. K. Rapp on Apr. 7, 1987.
The principle focus of the Rapp patent is to reduce power dissipation by the discriminator. However, low power dissipation is not the only criterion by which a circuit is evaluated. With the increasing demand for high frequency signal switching, it becomes desirable to have a level discriminator circuit that has fast response time. Therefore, an object of the present invention is to provide a high speed CMOS logic level discriminator circuit. However, it is a related object of this invention to provide fast logic level discriminator circuit which has low power dissipation.